NDLI: CMOS differential neural amplifier with high input impedance

Content Provider	IEEE Xplore Digital Library
Author	Rummens, F. Renaud, S. Lewis, N.
Copyright Year	2015
Description	Author affiliation: IMS, Talence, France (Renaud, S.) \|\| IMS, Univ. Bordeaux, Talence, France (Rummens, F.) \|\| Bordeaux INP, IMS, Pessac, France (Lewis, N.)
Abstract	We present a CMOS differential neural amplifier with high input impedance, which topology is inspired by the instrumentation amplifier. The miniaturization of the MEAs goes with an increase of the electrodes impedance and necessitates high input impedance neural amplifiers; otherwise it results in a significant loss of signal and low SNR. The circuit presented here is designed on a 0.35 μm CMOS technology. Two versions are described which capacitive input impedance is 1 pF. One is robust to high input offset and consumes 13.5 μA; the other one is more sensitive to offset but consumes only 3.7 μA. Both generate less than 7 $μV_{RMS}$ input-referred noise and their NEF figures are respectively 8.4 and 3.66. These features are competitive in view of the literature on neural amplifiers, while the circuit was specifically designed to present a high input impedance.
Starting Page	1
Ending Page	4
File Size	274609
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7182037
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Impedance Electrodes Noise Standards Capacitors Gain Topology MEA impedance neural amplifier instrumentation amplifier input impedance
Content Type	Text
Resource Type	Article

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