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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Amaricai, A. Gavriliu, C.-E. Boncalo, O. |
| Copyright Year | 2014 |
| Description | Author affiliation: Comput. Eng. Dept., Univ. Politeh. Timisoara, Timisoara, Romania (Amaricai, A.; Gavriliu, C.-E.; Boncalo, O.) |
| Abstract | This paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used pre-processing method, for a wide variety of image processing algorithms, such as feature detection, motion tracking, image registration, etc.. It relies on a series of sequential steps, each processing an image outputted by the previous step. The purpose of the sliding window is to avoid storing intermediate results of processing stages in the external FPGA memory or to avoid utilize large line buffers typically implemented with BRAM blocks. Therefore, the entire processing pipeline benefits from data locality. Implementation results for Virtex5 and Spartan-6 devices show that the proposed solution has very good performance (more than 130 fps for 1280×720 images in Xilinx Spartan-6) with significant less BRAM usage with respect to other approaches. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 468752 |
| Page Count | 4 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927402 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Computer architecture Field programmable gate arrays Smoothing methods Buffer storage Pipelines Clocks Image processing Harris's algorithm corner detection |
| Content Type | Text |
| Resource Type | Article |
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