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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nakatsuka, H. Tanaka, Y. Thiem Van Chu Takamaeda-Yamazaki, S. Kise, K. |
| Copyright Year | 2014 |
| Description | Author affiliation: Nara Inst. of Sci. & Technol., Nara, Japan (Takamaeda-Yamazaki, S.) || Tokyo Inst. of Technol., Tokyo, Japan (Nakatsuka, H.; Tanaka, Y.; Thiem Van Chu; Kise, K.) |
| Abstract | Soft processors have been commonly used in FPGAbased designs to perform various useful functions. Some of these functions are not performance-critical and required to be implemented using very few FPGA resources. For such cases, it is desired to reduce circuit area of the soft processor as much as possible. This paper proposes Ultrasmall, a small soft processor for FPGAs. Ultrasmall supports a subset of the MIPS-I ISA and is designed for microcontrollers in FPGA-based SoCs. Ultrasmall employs an area efficient architecture to minimize the use of FPGA resources. While supporting the 32-bit ISA, Ultrasmall adopts the 2-bit wide serial ALU architecture. This approach significantly reduces the amount of FPGA resource usage. In addition to the device-independent optimizations for any FPGAs, we apply primitives-based optimizations for the Xilinx Spartan-3E FPGA series with 4-input LUTs, thereby further reducing the total number of occupied slices. The evaluation result shows that, on the Xilinx Spartan-3E XC3S500E FPGA, Ultrasmall occupies only 137 slices which is 84% of the number of occupied slices of Supersmall, a very small soft processor with the same design concept as Ultrasmall. On the other hand, in term of performance, Ultrasmall is 2.9× faster than Supersmall. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 218832 |
| Page Count | 4 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927387 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Field programmable gate arrays Shift registers Hardware Multiplexing Table lookup Optimization |
| Content Type | Text |
| Resource Type | Article |
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