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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen Yang Leibo Liu Yansheng Wang Shouyi Yin Peng Cao Shaojun Wei |
| Copyright Year | 2014 |
| Description | Author affiliation: Inst. of Microelectron., Tsinghua Univ., Beijing, China (Chen Yang; Leibo Liu; Yansheng Wang; Shouyi Yin; Shaojun Wei) || IC Sch., Southeast Univ., Nanjing, China (Peng Cao) |
| Abstract | This paper proposes three configuration approaches to improve computing efficiency of a coarse-grained reconfigurable array, including input data relocation, line-based context switching, and loop interval minimization. These proposed approaches fully exploit the parallelism and pipelining of the reconfigurable array, which reduce interval latency when switching the configuration contexts, and therefore greatly enhance computing efficiency. These proposed techniques are used in a coarse-grained reconfigurable multimedia system (REMUS). Measured results show that, owing to the proposed approaches, REMUS can achieve 1080p@30fps performance for H.264 high profile video decoding under 200MHz working frequency. When normalized to the same technology, REMUS outperforms XPP-III 6.98x in energy efficiency. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 449644 |
| Page Count | 4 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927439 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Context Arrays Switches Decoding Clocks Pipelines |
| Content Type | Text |
| Resource Type | Article |
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