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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Blanchardon, A. Chotin-Avot, R. Mehrez, H. Amouri, E. |
| Copyright Year | 2014 |
| Description | Author affiliation: Sorbonne Univ., Paris, France (Blanchardon, A.; Chotin-Avot, R.; Mehrez, H.; Amouri, E.) |
| Abstract | The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous hardware redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (-6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max). |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 592712 |
| Page Count | 4 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927389 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Field programmable gate arrays Multiplexing Redundancy Delays Hardware Integrated circuit interconnections |
| Content Type | Text |
| Resource Type | Article |
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