NDLI: A scalable, high-performance customized priority queue

Content Provider	IEEE Xplore Digital Library
Author	Muhuan Huang Lim, K. Cong, J.
Copyright Year	2014
Description	Author affiliation: Hewlett Packard Labs., CA, USA (Lim, K.) \|\| Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA (Muhuan Huang; Cong, J.)
Abstract	Priority queues are abstract data structures where each element is associated with a priority, and the highest priority element is always retrieved first from the queue. The data structure is widely used within databases, including the last stage of a merge-sort, forecasting read-ahead I/O to stream data for the merge-sort, and replacement selection sort. Typical software implementations use a balanced binary tree-based structure, providing O(log N) time for both enqueue and dequeue operations. To improve the performance, we propose several scalable and high-speed FPGA-based implementations of a priority queue. Our insight is that the above listed applications primarily use priority queues through “replace” operations, which remove the highest priority element and place a new element into the queue. Thus, our designs are customized for this operation, allowing for a simple and scalable architecture. We implement three priority queue designs, including use of a register-based array, register-based tree, and BRAM-based tree, which have different benefits and trade-offs of throughput, frequency, and maximum size. More importantly, all designs achieve O(1) time between replace operations. To incorporate the best aspects of our designs, we propose a Hybrid Priority Queue (H-PQ), which combines a register-based array with multiple BRAM-based trees. This design provides, on average, very fast access times to the top items in the queue (through the register-based array), while scaling to large priority queue sizes (through the BRAM-based trees). In our evaluations, we find that H-PQ achieves 4.3x speedup and 21.5x energy efficiency, compared with the Xeon CPU implementations.
Starting Page	1
Ending Page	4
File Size	2207927
Page Count	4
File Format	PDF
ISBN	9783000446450
DOI	10.1109/FPL.2014.6927413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Technical University of Munich (TUM)
Subject Keyword	Throughput Field programmable gate arrays Arrays Registers Clocks Software Database systems
Content Type	Text
Resource Type	Article

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