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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jian Gong Tao Wang Jiahua Chen Haoyang Wu Fan Ye Songwu Lu Cong, J. |
| Copyright Year | 2014 |
| Description | Author affiliation: Center for Energy-Efficient Comput. & Applic., Peking Univ., Beijing, China (Jian Gong; Tao Wang; Jiahua Chen; Haoyang Wu; Fan Ye; Songwu Lu; Cong, J.) |
| Abstract | A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance host-FPGA PCIe communication library holds the key to broadening the use of FPGA accelerators. In this paper we target efficiency and flexibility as two important features in such a library. We discuss the challenges in providing these features, and present our solution to these challenges. We propose EPEE, an efficient and flexible host-FPGA PCIe communication library and describe its design. We implemented EPEE in various generations of Xilinx FPGAs with up to 26.24 Gbps half-duplex and 43.02 Gbps full-duplex aggregate throughput in the PCIe Gen2 X8 mode; these are at the best utilization levels that a host-FPGA PCIe library can achieve. The EPEE library has been integrated into four different FPGA applications with different data usage patterns in various institutes. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 171803 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927459 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Field programmable gate arrays Libraries Software Hardware Throughput IP networks Registers Communication library FPGA PCIe Efficiency Flexibility |
| Content Type | Text |
| Resource Type | Article |
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