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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pietras, M. |
| Copyright Year | 2014 |
| Description | Author affiliation: Comput. Sci. & Inf. Technol., West Pomeranian Univ. of Technol., Szczecin, Poland (Pietras, M.) |
| Abstract | The transition from a neural network simulation model to its hardware representation is a complex process, which touches computations precision, performance and effective architecture implementation issues. Presented neural processing accelerator involves neural network sectioning, precision reduction and weight coefficients parsing (arrangements) in order to increase efficiency and maximize FPGA hardware resources utilization. Particular attention has been devoted on to ANN conversion methods designed for a system based on neural processing units and related with this process redundant calculations and empty neurons generation. In addition, this paper describes the FPGA-based Neural Processing Accelerator architecture benchmark for real example implementation of a pattern recognition neural network. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 255533 |
| Page Count | 4 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927383 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Biological neural networks Neurons Hardware Computational modeling Artificial neural networks Field programmable gate arrays Computer architecture Redundancy FPGA NPU Accelerator Architecture Kintex 7 Hardware Neural Network Reduced floating-point Matlab ANN Toolbox |
| Content Type | Text |
| Resource Type | Article |
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