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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nguyen, T.D.A. Kumar, A. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore (Nguyen, T.D.A.; Kumar, A.) |
| Abstract | FPGA-based heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) are becoming quite popular for high performance embedded systems because of their powerful computational ability and relatively flexible architecture to adapt to unexpected system requirement changes. However, with the insatiable demands of supporting an extensive range of applications beyond the limited resources of FPGA chip and shorter time-to-market, many research works on partially reconfigurable (PR) FPGA architectures have been conducted to fulfill the needs. Those have yet to fully provide a versatile framework to exploit the flexibility of PR such as hardware/software task migration and bitstream relocation; more importantly, the on-chip debug features to access all processors currently loaded in the system are compromised because of the lack of native-support from vendor tools. In this paper, a novel PR-HMPSoC architecture for dynamic FPGA-based embedded system is proposed to provide solutions for all of the above issues. The results from the experimental system consisting of one static Microblaze and three PR Microblaze/hardware accelerators connected by a Network-on-Chip show that the architecture is very promising with just 8% reduction in operating frequency. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 635548 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783000446450 |
| DOI | 10.1109/FPL.2014.6927492 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-02 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Technical University of Munich (TUM) |
| Subject Keyword | Program processors Hardware Field programmable gate arrays Clocks Loading Memory management task migration FPGA partial reconfiguration multiprocessor heterogeneous debug bitstream relocation |
| Content Type | Text |
| Resource Type | Article |
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