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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Asokan, A. Todri-Sanial, A. Bosio, A. Dilillo, L. Girard, P. Pravossoudovitch, S. Virazel, A. |
| Copyright Year | 2014 |
| Description | Author affiliation: LIRMM, Univ. of Montpellier II, Montpellier, France (Asokan, A.; Todri-Sanial, A.; Bosio, A.; Dilillo, L.; Girard, P.; Pravossoudovitch, S.; Virazel, A.) |
| Abstract | Ongoing technology scaling has increased delay defects in integrated circuits. Some of the delay defects are due to crosstalk, supply noise, process variations, etc. They degrade the performance and field reliability of circuits. However, testing the circuits with path delay patterns under worst-case conditions helps to detect such defects. Estimation of patterns with worst-case path delay becomes difficult using the conventional techniques due to their unpredictable behavior. In this paper, we first describe the problem and then propose our approach in identifying a worst-case path delay pattern under the impact of process variations and supply noise. A delay probability metric ispresented in this work, for an efficient identification of worst-case path delay pattern, which is the basis of our ranking method. The simulation results of ITC'99 benchmark circuits show the feasibility of our delay probability metric. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 226 |
| Ending Page | 231 |
| File Size | 204901 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479937653 |
| DOI | 10.1109/ISVLSI.2014.42 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-07-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Tin Integrated circuit interconnections Noise Logic gates Transistors supply noise (SN) delay defects delay probability metric process variations (PV) |
| Content Type | Text |
| Resource Type | Article |
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