NDLI: Function Extraction from Arithmetic Bit-Level Circuits

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2015 IEEE Computer Society Annual Symposium on VLSI

2014 IEEE Computer Society Annual Symposium on VLSI

Table of contents

Message from the General and Program Chairs

Technical Program Committee

Steering Committee

Additional Reviewers

Variation Aware Design of Post-Silicon Tunable Clock Buffer

Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency

Regulator-Gating Methodology with Distributed Switched Capacitor Voltage Converters

Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits

PUF Interfaces and their Security

Post-Silicon Validation and Calibration of Hardware Security Primitives

Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization

A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture

Experiments with High Speed Parallel Cubing Units

A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation

Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving Computation

A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory Array

FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs

Neuromemristive Extreme Learning Machines for Pattern Classification

A New Walsh Hadamard Transform Architecture Using Current Mode Circuit

A Transient-Enhanced Capacitorless LDO Regulator with improved Error Amplifier

Memristor Crossbar Based Programmable Interconnects

Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation

Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff

Slicing Floorplans with Handling Symmetry and General Placement Constraints

Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders

Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication

Computational Architectures Based on Coupled Oscillators

A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing

An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics

Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect Transistors

Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach

Removing the Root of Trust: Secure Oblivious Key Establishment for FPGAs

Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking

Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis

Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation

An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Session Based Core Test Scheduling for 3D SOCs

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties

Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-Bond Test

Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage

A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise

Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements

Dynamic Phase-Based Optimization of Embedded Systems

A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology

Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits

Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture

Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications

A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT Transducers

A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C

A Compact CMOS Ring Oscillator with Temperature and Supply Compensation for Sensor Applications

Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults

Where is the Achilles Heel under Circuit Aging

Chip Health Monitoring Using Machine Learning

Toward Holistic Modeling, Margining and Tolerance of IC Variability

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices

Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed

A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET

FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes

OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis

Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults

Layout-Aware Selection of Trace Signals for Post-Silicon Debug

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits

Improving GA-Based NoC Mapping Algorithms Using a Formal Model

Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN

Function Extraction from Arithmetic Bit-Level Circuits

Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization

Characterization of MWCNT VLSI Interconnect with Self-Heating Induced Scatterings

High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation Arrays

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs

Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

Memristor Modeling -- Static, Statistical, and Stochastic Methodologies

Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices

5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes

A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures

Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores

System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks

Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis

Achieving High-Performance Video Analytics with Lightweight Cores and a Sea of Hardware Accelerators

Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing

Big Data Processing with FPGA Supercomputers: Opportunities and Challenges

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design

Glitch Power Reduction via Clock Skew Scheduling

On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery

Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors

Glitch Resistant Private Circuits Design Using HORNS

Towards Making Private Circuits Practical: DPA Resistant Private Circuits

LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches

A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach

An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies

Processor Design with Asymmetric Reliability

"Green" On-chip Inductors in Three-Dimensional Integrated Circuits

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

Multi-level, Memory-Based Logic Using CMOS Technology

Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation

Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits

Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline

A Fast Hypergraph Bipartitioning Algorithm

A Graph-Based 3D IC Partitioning Technique

Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

2012 IEEE Computer Society Annual Symposium on VLSI

2011 IEEE Computer Society Annual Symposium on VLSI

2010 IEEE Computer Society Annual Symposium on VLSI

2009 IEEE Computer Society Annual Symposium on VLSI

2008 IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

Function Extraction from Arithmetic Bit-Level Circuits

Content Provider	IEEE Xplore Digital Library
Author	Ciesielski, M. Brown, W. Duo Liu Rossi, A.
Copyright Year	2014
Description	Author affiliation: Univ. of Massachusetts, Amherst, MA, USA (Ciesielski, M.; Brown, W.; Duo Liu) \|\| Lab. STICC, Univ. de Bretagne-Sud, Lorient, France (Rossi, A.)
Abstract	The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic function from the circuit is accomplished by transforming the expression at the primary outputs into an expression at the primary inputs. Experimental results show application of the method to certain classes of large arithmetic circuits.
Sponsorship	IEEE Comput. Soc.
Starting Page	356
Ending Page	361
File Size	315304
Page Count	6
File Format	PDF
e-ISBN	9781479937653
DOI	10.1109/ISVLSI.2014.43
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Integrated circuit modeling Polynomials Computational modeling Mathematical model Adders arithmetic verification Formal verification arithmetic circuits
Content Type	Text
Resource Type	Article

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