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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yier Jin |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA (Yier Jin) |
| Abstract | Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. To balance trustworthiness and testability, a new design-for-security (DFS) methodology is proposed which, through the modification of scan chain structure, can achieve high security without compromising the testability of the inserted scan structure. To support the task of secure scan chain insertion, a method of scan chain reshuffling is introduced. Using an AES encryption core as the testing platform, we elaborated the security assessment procedure as well as the DFS technique in balancing security and testability of cryptographic circuits. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 19 |
| Ending Page | 24 |
| File Size | 352222 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479937653 |
| DOI | 10.1109/ISVLSI.2014.54 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-07-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Security Discrete Fourier transforms Built-in self-test Logic gates Sensitivity Hardware Hardware Trust Design-for-Security |
| Content Type | Text |
| Resource Type | Article |
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