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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jungmin Park Tyagi, A. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Jungmin Park; Tyagi, A.) |
| Abstract | The differential power analysis (DPA) attack is a well known major threat to cryptographic devices such as smart cards or other embedded systems. Quantification of resistance or robustness of a cryptographic device against the differential power analysis attack is lacking. We propose a DPA effectiveness (inverse of robustness) metric. We develop a logic graph based computational method for DPA effectiveness. Based on our insights with DPA effectiveness measures of an adder we develop a countermeasure. It enhances the proposed DPA resistance metric in normal 0-private circuits to the level of t-private circuits for t ≥ 1 at a smaller area and delay overhead. It deploys EXOR sum-of-products (ESOP) expressions to make the power consumption independent of input values or intermediate values. The logic synthesis system SIS was modified to incorporate both the proposed DPA effectiveness metric computation and the DPA-resistance transformation. The experiments show that the area and delay overhead of the proposed design method are 59.8% and 19.4%, respectively, compared to the original ESOP circuits averaged over MCNC benchmark suite. This, however, still takes 37.7% less area and 6.4% lower delay compared to 1-private implementation of the MCNC benchmark suite while maintaining the same DPA resistance. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 528 |
| Ending Page | 533 |
| File Size | 1016112 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479937653 |
| DOI | 10.1109/ISVLSI.2014.24 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-07-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitance Logic gates Adders Power demand Observability Switches Equations ESOP differential power analysis t-private circuit |
| Content Type | Text |
| Resource Type | Article |
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