NDLI: Glitch Resistant Private Circuits Design Using HORNS

Content Provider	IEEE Xplore Digital Library
Author	Gomathisankaran, M. Tyagi, A.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of North Texas, Denton, TX, USA (Gomathisankaran, M.) \|\| Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Tyagi, A.)
Abstract	Cryptographic algorithms and their specific instantiation in computing engines leak information both through information channels and physical channels (side-channels). CMOS circuits implementing these cryptographic algorithms engines leak information through its physical attributes. The overlooked vulnerabilities in communication, cryptographic, or other system protocols and software, leak computation internal state inadvertently. These are the explicitly designed computational channels which are Turing channels. An unintended, lower barrier leakage occurs, however, through the side channels or physical channels. An actual implementation of an abstract algorithm goes through a model refinement to include the physical properties of the underlying computing machinery. Since there are no constraints placed on many of the physical attributes not visible in the algorithm specification in an abstract model, any refinement is acceptable. This is where the problem occurs. Some of these implementations reveal significant details about the private control and data flow of the underlying computation. In general there are two approaches to solve this problem. First approach is to design cryptographic algorithms which can tolerate some information leakage. Second approach is to remove the correlation between the leaked information and the secret. We propose a novel circuit design technique which uses the second approach.
Sponsorship	IEEE Comput. Soc.
Starting Page	522
Ending Page	527
File Size	205825
Page Count	6
File Format	PDF
e-ISBN	9781479937653
DOI	10.1109/ISVLSI.2014.93
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Privacy Encryption Circuit synthesis Integrated circuit modeling Bandwidth glitch resistant private circuits private circuits tamper resistant circuits secure circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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