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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ahmad, T.B. Ciesielski, M. |
| Copyright Year | 2014 |
| Description | Author affiliation: ECE Dept., UMASS Amherst, Amherst, MA, USA (Ahmad, T.B.; Ciesielski, M.) |
| Abstract | While multi-core computing has become pervasive, scaling single core computations to multi-core computations remains a challenge. This paper aims to accelerate RTL and functional gate-level simulation in the current multi-core computing environment. This work addresses two types of partitioning schemes for multi-core simulation: functional, and domain-based. We discuss the limitations of functional partitioning, offered by new commercial multi-core simulators to speedup functional gate-level simulations. We also present a novel solution to increase RTL and functional gate-level simulation performance based on domain partitioning. This is the first known work that improves simulation performance by leveraging open source technology against commercial simulators. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 619 |
| Ending Page | 624 |
| File Size | 285313 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479937653 |
| DOI | 10.1109/ISVLSI.2014.47 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-07-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Multicore processing Hardware design languages Computational modeling Parallel processing Integrated circuit modeling Data models Verilog Simulation Multi-core ASIC Opencores RTL Gate-level |
| Content Type | Text |
| Resource Type | Article |
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