NDLI: A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing

Content Provider	IEEE Xplore Digital Library
Author	Bose, A. Ghosal, P. Mohanty, S.P.
Copyright Year	2014
Description	Author affiliation: Indian Inst. of Eng. Sci. & Technol., Howrah, India (Bose, A.; Ghosal, P.) \|\| Univ. of North Texas, Denton, TX, USA (Mohanty, S.P.)
Abstract	Due to the limitations of traditional bus based systems, Network-on-Chip (NoC) has evolved as the most dominanttechnology in the paradigm of communication-centric revolution, where, besides the computation, inter-communication between the cores is an indispensable aspect of a SoC. Furthermore, the emergence of three dimensional integrated circuits (3D-ICs) has resulted in better performance, functionality, and packaging density compared to traditional planar ICs. The amalgamation of these two technologies, the 3D NoC architecture, can combine the benefits of these two new domains to offer an unprecedentedperformance gain. In this paper, we present a new 3D topological NoC design based on the butterfly fat tree (BFT) topology with an efficient table based uniform routing algorithm for 3D NoC. Extensive simulation experiments have been performed for BFT and compared to mesh, torus, butterfly and flattened butterfly topologies against four performance metrics viz. overall average latency, overall average acceptance rate, overall minimum acceptance rate, and average hop counts. There are significant latency improvements of 43-89 %, 83-88 %, 46-96 %, and 31-95 % over other topologies respectively. Average hop count is improved by 30 % and 13 % over mesh and torus. Also, there are improvements in average acceptance rate and minimum acceptance rate of 1-8 % and 5-14 % respectively for flattened butterfly and 6-9 % and 6-13 % over torus. Results evidently show that BFT is a very good choice for low network latency and faster communication.
Sponsorship	IEEE Comput. Soc.
Starting Page	136
Ending Page	141
File Size	625405
Page Count	6
File Format	PDF
e-ISBN	9781479937653
DOI	10.1109/ISVLSI.2014.51
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Three-dimensional displays Topology IP networks Computer architecture Network topology System-on-chip NoC Architecture 3D Network on Chip Uniform Hopping Distance Table Based Routing Low Network Latency
Content Type	Text
Resource Type	Article

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