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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ratkovic, I. Palomar, O. Stanic, M. Unsal, O. Cristal, A. Valero, M. |
| Copyright Year | 2014 |
| Abstract | Selecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power (metrics of interest) depends on the phase of the design flow and the fidelity of the models. In this research, we use design space exploration of low-power adders as a case study for comparative analysis of two estimation flows: Physical layout Aware Synthesis (PAS) and Place and Route (PnR). We study and compare post-PAS and post-PnR estimations of the metrics of interest and the impact of various design parameters and input switching activity factor (αI). Adders are particularly interesting for this study because they are fundamental microprocessor units, and their design involves many parameters that create a vast design space. We show cases when the post-PAS and post-PnR estimations could lead to different design decisions, especially from a low-power designer point of view. Our experiments reveal that post-PAS results underestimate the side-effects of clock-gating, pipelining, and extensive timing optimizations compared to post-PnR results. We also observe that PnR estimation flow sometimes reports counterintuitive results. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 118 |
| Ending Page | 123 |
| File Size | 367092 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479937653 |
| DOI | 10.1109/ISVLSI.2014.14 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-07-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Estimation Adders Clocks Timing Optimization Pipeline processing Low-Power Estimation method Adder Design Space Exploration Place and Route Physical Layout Aware Synthesis |
| Content Type | Text |
| Resource Type | Article |
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