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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sei-Hyung Ryu Krishnaswami, S. Hull, B. Richmond, J. Agarwal, A. Hefner, A. |
| Copyright Year | 2006 |
| Description | Author affiliation: Cree, Inc., Durham, NC (Sei-Hyung Ryu; Krishnaswami, S.; Hull, B.; Richmond, J.; Agarwal, A.) |
| Abstract | In this paper, we report 4H-SiC power DMOSFETs capable of blocking 10 kV. The devices were scaled up to 5 A, which is a factor of 25 increase in device area compared to the previously reported value. The devices utilized 100 mum thick n-type epilayers with a doping concentration of 6 times $10^{14}$ $cm^{-3}$ for drift layers, and a floating guard ring based edge termination structure was used. The gate oxide layer was formed by thermal oxidation at 1175 degC, followed by an NO anneal. A peak effective channel mobility of 13 $cm^{2}/Vs$ was extracted from a test MOSFET with a W/L of 150 mum / 150 mum, built adjacent to the power DMOSFETs. A 4H-SiC DMOSFET with an active area of 0.15 cm showed a specific on-resistance of 111 $mOmega-cm^{2}$ at room temperature with a gate bias of 15 V. The device shows a leakage current of 3.3 muA, which corresponds to a leakage current density of 11 $muA-cm^{-2}$ at a drain bias of 10 kV |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 3071714 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780397142 |
| DOI | 10.1109/ISPSD.2006.1666122 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-06-04 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Voltage Nitrogen Doping Electrodes Dielectric substrates Aluminum Working environment noise Temperature Implants Silicon |
| Content Type | Text |
| Resource Type | Article |
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