Please wait, while we are loading the content...
Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Agarwal, A. Sei-Hyung Ryu Das, M. Lipkin, L. Palmour, J. Saks, N. |
| Copyright Year | 2001 |
| Description | Author affiliation: Cree Inc., Durham, NC, USA (Agarwal, A.) |
| Abstract | This paper describes the design and fabrication of 4H-SiC, n-channel Power MOSFETs. For the first time, we have achieved 350 V, 10 A (V/sub F/=4.4 V) devices with an active area of 0.105 cm/sup 2/ (3.3 mm /spl times/3.3 mm). This represents a specific on-resistance of 43 m/spl Omega//spl middot/cm/sup 2/ for a cell pitch of 25 /spl mu/m (160,000 cells/cm/sup 2/). We have also achieved R/sub on,sp/=23 m/spl Omega//spl middot/cm/sup 2/ on smaller cells with a cell pitch of 16 /spl mu/m (390,000 cells/cm/sup 2/). An important issue in 4H-SiC MOSFETs is extremely low effective channel mobility (/spl mu//sub neff/) in the implanted p-well regions. It is shown that Al-implanted p-wells require at least 1600/spl deg/C activation anneal to achieve reasonable bulk hole mobility. Annealing at high temperatures causes surface roughness which degrades /spl mu//sub neff/ compared to low power MOSFETs made on a p-epilayer. NO annealing of the gate oxide and a buried channel structure are used for increasing /spl mu//sub neff/. A Buried channel (BC) structure with 1.7/spl times/10/sup 12/ cm/sup -2/ charge in the channel showed a high /spl mu//sub neff/ (195 cm/sup 2//V/spl middot/s) utilizing bulk buried channel, but resulted in a normally-on device. However, it is shown that by controlling the charge in the BC layer, a normally-off device with a high /spl mu//sub neff/ can be produced. |
| Sponsorship | Inst. Electr. Eng. Japan |
| Starting Page | 183 |
| Ending Page | 186 |
| File Size | 477905 |
| Page Count | 4 |
| File Format | |
| ISBN | 4886860567 |
| ISSN | 10636854 |
| DOI | 10.1109/ISPSD.2001.934585 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-06-07 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Inst. Of Electrical Engineers Japan |
| Subject Keyword | MOSFETs Annealing Implants Voltage Doping Aluminum Dielectrics Silicon carbide FETs Laboratories |
| Content Type | Text |
| Resource Type | Article |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|