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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pan, R. Todd, B. Pinghai Hao Higgins, R. Robinson, D. Drobny, V. Weidong Tian Jianglin Wang Mitros, J. Huber, M. Pillai, S. Pendharkar, S. |
| Copyright Year | 2006 |
| Description | Author affiliation: Texas Instruments Inc., Dallas, TX (Pan, R.; Todd, B.; Pinghai Hao; Higgins, R.; Robinson, D.; Drobny, V.; Weidong Tian; Jianglin Wang; Mitros, J.; Huber, M.; Pillai, S.; Pendharkar, S.) |
| Abstract | This paper describes the integration of the 20V complementary drain-extended MOS (DECMOS) and fully isolated drain-extended NMOS (DENMOS) transistors into a high-volume 0.13mum CMOS technology with two additional masks. The 20V devices were optimized for Rsp-BVdss performance without compromising the advanced 1.5V CMOS performance in the 0.35mum pitch copper, low-K dielectric process flow. This cost-effective process is very competitive for the power management (PM) chip design of portable devices |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 897248 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780397142 |
| DOI | 10.1109/ISPSD.2006.1666143 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-06-04 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Voltage BiCMOS integrated circuits System-on-a-chip CMOS technology Isolation technology MOS devices MOSFETs Transistors CMOS process Copper |
| Content Type | Text |
| Resource Type | Article |
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