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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rusu, S. Muljono, H. Ayers, D. Tam, S. Wei Chen Martin, A. Shenggao Li Vora, S. Varada, R. Wang, E. |
| Copyright Year | 2014 |
| Description | Author affiliation: Intel, Santa Clara, CA, USA (Rusu, S.; Muljono, H.; Ayers, D.; Tam, S.; Wei Chen; Martin, A.; Shenggao Li; Vora, S.; Varada, R.; Wang, E.) |
| Abstract | The next-generation enterprise $Xeon^{®}$ server processor has 15 dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system topologies. The processor has 4.31B transistors in a high-κ metal-gate tri-gate 22nm CMOS technology with 9 metal layers [2]. The design supports a wide array of product offerings with thermal design power ranging from 40 to 150W and frequencies ranging from 1.4 to 3.8GHz. Fig. 5.4.1(a) shows the processor block diagram. The floorplan (Fig. 5.4.1(b)) is driven by the ring bus routability and latency, as well as the chop requirements to smaller core counts. The cores and associated L3 cache are organized in columns of five, with the ring bus segment embedded. The fully populated die has 15-cores in three columns. The 10-core chop removes the rightmost $3^{rd}$ column and its dedicated top and bottom IOs. CMOS muxes embedded in the ring bus are programmably operable in a 2-or-3-columns configuration. The 6-core chop removes the $2^{nd}$ and $4^{th}$ rows from the 10-core die. |
| Starting Page | 102 |
| Ending Page | 103 |
| File Size | 1461024 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479909186 |
| ISSN | 01936530 |
| e-ISBN | 9781479909209 |
| DOI | 10.1109/ISSCC.2014.6757356 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-02-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Program processors Arrays Clocks Transistors CMOS integrated circuits Capacitance System-on-chip |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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