NDLI: 13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V applications

Content Provider	IEEE Xplore Digital Library
Author	Yen-Huei Chen Wei-Min Chan Wei-Cheng Wu Hung-Jen Liao Kuo-Hua Pan Jhon-Jhy Liaw Tang-Hsuan Chung Quincy Li Chang, G.H. Chih-Yung Lin Mu-Chi Chiang Shien-Yang Wu Natarajan, S. Chang, J.
Copyright Year	2014
Description	Author affiliation: TSMC, Hsinchu, Taiwan (Yen-Huei Chen; Wei-Min Chan; Wei-Cheng Wu; Hung-Jen Liao; Kuo-Hua Pan; Jhon-Jhy Liaw; Tang-Hsuan Chung; Quincy Li; Chang, G.H.; Chih-Yung Lin; Mu-Chi Chiang; Shien-Yang Wu; Natarajan, S.; Chang, J.)
Abstract	FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM $V_{DDMIN}.$ However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With the process variations, the strength of PU transistor can be much stronger than the PG transistor. A stronger PU transistor increases read stability of the SRAM bitcell but it degrades the write margin significantly and results in worse $write-V_{DDMIN}$ issue. Figure 13.5.1(a) shows a contention condition between PU and PG transistors of a 6T-SRAM bitcell for the write operation. During the write operation, the PU transistor impedes the ability of the PG transistor to pull the storage node (S) from $V_{DD}$ to ground. The bitcell may suffer a write failure at the stronger PU with weaker PG condition caused by the device variations. Two techniques have been proposed to improve the high density SRAM bitcell write $V_{DDMIN}:$ 1) negative bit-line voltage (NBL) to increase the strength of PG transistor and 2) lower cell $V_{DD}$ (LCV) to weaken PU transistor strength [1-5]. Compared to the conventional techniques, this work develops a suppressed-coupling-signal negative bitline (SCS-NBL) scheme and a write-recovery-enhancement $lower-cell-V_{DD}$ (WRE-LCV) scheme for write assist without the concern of reliability at higher $V_{DD}$ operating region. A comparison of the effectiveness of the two design techniques is also performed. Figure 13.5.1(b) shows the layout view of the high-density 6T-SRAM bit-cell with $0.07μm^{2}$ area in a 16nm high-k metal-gate FinFET technology. To minimize area, we set the geometric ratio of PU, PG, and PD transistors all equal to one. With the two developed write-assist circuits, the overall $V_{DDMIN}$ improvement can be over 300mV in a 128Mb SRAM test-chip.
Starting Page	238
Ending Page	239
File Size	1593421
Page Count	2
File Format	PDF
ISBN	9781479909186
ISSN	01936530
e-ISBN	9781479909209
DOI	10.1109/ISSCC.2014.6757416
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-02-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Couplings Logic gates High K dielectric materials FinFETs CMOS integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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