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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Salem, L.G. Mercier, P.P. |
| Copyright Year | 2014 |
| Description | Author affiliation: Univ. of California, San Diego, La Jolla, CA, USA (Salem, L.G.; Mercier, P.P.) |
| Abstract | The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. Dynamic voltage scaling (DVS) can help achieve these goals in load circuits, though generally at the expense of increased DC-DC converter size (through use of external inductors) or loss (through linear regulation). While switched-capacitor (SC) DC-DC converters can offer conversion in small fully integrated form factors [1-5], their efficiencies are only high at discrete ratios between the input and output voltages. To increase an SC converter efficiency across its output voltage range, multiple conversion ratios can be utilized to realize a finer output voltage resolution. For instance, many converters employ a small handful of conversion ratios [1-4]. However, more conversion ratios are generally necessary to achieve high efficiency across the wide output range necessary for DVS, as converter efficiencies can otherwise fall by more than 20% between unloaded ratios [1-4]. Unfortunately, increasing the number of ratios beyond a small handful using standard topologies can significantly increase the number of components, escalating converter complexity and adding losses in the additional switching elements. To overcome this, a successive approximation (SAR) SC topology was proposed in [6] which cascades several 2:1 SC stages to provide a large number of conversion ratios with minimal hardware overhead. However, the linear cascading of stages introduces cascaded losses, limiting overall efficiency. For example, the minimum $R_{out}$ is more than 30X $R_{out}$ of a similar ratio Series-Parallel topology using the same silicon area. Additionally, current density is limited to that of a single stage, and capacitance utilization can be low for many conversion ratios. |
| Starting Page | 88 |
| Ending Page | 89 |
| File Size | 10381413 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479909186 |
| ISSN | 01936530 |
| e-ISBN | 9781479909209 |
| DOI | 10.1109/ISSCC.2014.6757350 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-02-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Topology Switches Capacitors Capacitance Current measurement Voltage measurement System-on-chip |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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