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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yejoong Kim Wanyeong Jung Inhee Lee Qing Dong Henry, M. Sylvester, D. Blaauw, D. |
| Copyright Year | 2014 |
| Description | Author affiliation: Univ. of Michigan, Ann Arbor, MI, USA (Yejoong Kim; Wanyeong Jung; Inhee Lee; Qing Dong; Henry, M.; Sylvester, D.; Blaauw, D.) |
| Abstract | Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC [2], which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: 1) static operation, since dynamic nodes are highly susceptible to PVT variations at low voltage; 2) contention-free transitions, since ratioed logic has poor robustness across the wide range of device $I_{ON}/I_{OFF}$ ratios incurred with voltage scaling; 3) single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty; 4) minimum or no area penalty compared to conventional flip-flops. |
| Starting Page | 466 |
| Ending Page | 467 |
| File Size | 19344248 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479909186 |
| ISSN | 01936530 |
| e-ISBN | 9781479909209 |
| DOI | 10.1109/ISSCC.2014.6757516 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-02-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Flip-flops Semiconductor device measurement Delays Energy efficiency Power measurement CMOS integrated circuits |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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