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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Meng-Fan Chang Jui-Jen Wu Tun-Fei Chien Yen-Chen Liu Ting-Chin Yang Wen-Chao Shen Ya-Chin King Chorng-Jung Lin Ku-Feng Lin Yu-Der Chih Natarajan, S. Chang, J. |
| Copyright Year | 2014 |
| Description | Author affiliation: TSMC, Hsinchu, Taiwan (Ku-Feng Lin; Yu-Der Chih; Natarajan, S.; Chang, J.) || Nat. Tsing Hua Univ., Hsinchu, Taiwan (Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin) |
| Abstract | Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time $(T_{AC})$ and low $RD-V_{DDMIN},$ particularly for devices powered by batteries or energy harvesters. The cross-point ReRAM [4-6] is meant for high capacities with high $RD-V_{DDMIN}$ and slow $T_{AC}.$ As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio $(R_{H}/R_{L})$ between the high-R state (HRS, $R_{H})$ and low-R state (LRS, $R_{L}).$ ReRAM also have a high $R_{L},$ which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM macro designs suffer: (1) small sensing margin (SM), limited $RD-V_{DDMIN},$ and slow $T_{AC}$ due to $high-R_{L}$ and small R-ratio; (2) increase in energy due to large set DC-current $(I_{DC-SET})$ resulting from wide set-time $(T_{SET})$ distribution. This study develops a swing-sample-andcouple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower $RD-V_{DDMIN}$ and 1.7× faster $T_{AC}$ across various $V_{DD},$ compared to conventional differential-input (CD) VSAs. To reduce >99% set energy, we use a 4T self-boost-write-termination (SBWT) scheme to cut off $I_{DC-SET}$ of $faster-T_{SET}$ devices, with an area penalty below 0.5%. A fabricated 28nm 1Mb ReRAM macro achieves $T_{AC}$ = 404ns at $V_{DD}$ = 0.27V and confirms the $I_{DC-SET}$ cut-off by SBWT. |
| Starting Page | 332 |
| Ending Page | 333 |
| File Size | 2764206 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479909186 |
| ISSN | 01936530 |
| e-ISBN | 9781479909209 |
| DOI | 10.1109/ISSCC.2014.6757457 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-02-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Logic gates CMOS integrated circuits Switches Nonvolatile memory Sensors Delays |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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