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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hyun-Woo Lee Junyoung Song Sang-Ah Hyun Seunggeun Baek Yuri Lim Jungwan Lee Minsu Park Haerang Choi Changkyu Choi Jinyoup Cha Jaeil Kim Hoon Choi Seungwook Kwack Yonggu Kang Jongsam Kim Junghoon Park Jonghwan Kim Jinhee Cho Chulwoo Kim Yunsaing Kim Jaejin Lee Byongtae Chung Sungjoo Hong |
| Copyright Year | 2014 |
| Description | Author affiliation: Korea Univ., Seoul, South Korea (Junyoung Song; Chulwoo Kim) || SK Hynix, Icheon, South Korea (Hyun-Woo Lee; Sang-Ah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jinyoup Cha; Jaeil Kim; Hoon Choi; Seungwook Kwack; Yonggu Kang; Jongsam Kim; Junghoon Park; Jonghwan Kim; Jinhee Cho; Yunsaing Kim; Jaejin Lee; Byongtae Chung; Sungjoo Hong) |
| Abstract | The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted. |
| Starting Page | 434 |
| Ending Page | 435 |
| File Size | 1550920 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479909186 |
| ISSN | 01936530 |
| e-ISBN | 9781479909209 |
| DOI | 10.1109/ISSCC.2014.6757502 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-02-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Random access memory Timing Graphics Phase locked loops Distortion measurement Power demand |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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