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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wee Liang Lien Tieng Ying Choke Ying Chow Tan Ming Kong Eng Chuan Low Dan Ping Li Liming Jin Huajiang Zhang Chin Heng Leow Soong Lin Chew Dasgupta, U. Chee Hong Yong Tian Bao Gao Geok Teng Ong Wee Guan Tan Weimin Shu Chee Lee Heng Shana'A, O. |
| Copyright Year | 2014 |
| Description | Author affiliation: MediaTek, Singapore, Singapore (Wee Liang Lien; Tieng Ying Choke; Ying Chow Tan; Ming Kong; Eng Chuan Low; Dan Ping Li; Liming Jin; Huajiang Zhang; Chin Heng Leow; Soong Lin Chew; Dasgupta, U.; Chee Hong Yong; Tian Bao Gao; Geok Teng Ong; Wee Guan Tan; Weimin Shu; Chee Lee Heng; Shana'A, O.) |
| Abstract | The popularity of the Near-Field Communication (NFC) system stems from being able to establish communication by merely being in the vicinity of another NFC device, an operation known as “tap and go”. An NFC device is quite complex: it has to support both ASK/BPSK modulation, variable data rates from 106kb/s to 848kb/s, different ASK modulation indices (8% to 100%), different card types (NFC-A/B/F), and various coding. It also has different operating modes such as Proximity-Inductively-Coupled Card (PICC) or card-emulation mode, Proximity-Coupled-Device (PCD) or reader mode and Peer-to-Peer (P2P) mode. Furthermore, some PCDs transmit NFC-A/B/F ASK data in a polling loop manner. Therefore, PICC receivers must support joint data-type detection for successful communication with such PCDs. The device shown in Fig. 9.1.1 supports all these operating modes and complies with ISO-14443, ISO-18092 and NFC Forum standards. The SoC has an ultra-low current receiver, a digital transmitter with a 250mA-maximum-current-drive Class-D PA, a Single-Wire Protocol (SWP) supporting two external UICC SIM cards and one micro-SD chip, an energy-harvesting rectifier unit, an agile synthesizer, and a digital modem. Traditionally, two separate receivers with respective synthesizers and clock recovery/generation circuits are adopted for PICC, PCD and P2P modes [1,2]. In addition, three parallel analog demodulators are needed (one each for NFC-A, B and F) to support joint data-type detection, thus increasing die area significantly. The focus of this paper is the adoption of a single receiver with one reconfigurable PLL to support all NFC modes for compact die area. |
| Starting Page | 158 |
| Ending Page | 159 |
| File Size | 2401969 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479909186 |
| ISSN | 01936530 |
| e-ISBN | 9781479909209 |
| DOI | 10.1109/ISSCC.2014.6757380 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-02-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase locked loops System-on-chip Receivers Amplitude shift keying Clocks Detectors |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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