NDLI: F2: Ultra-low voltage VLSIs for energy efficient systems

Content Provider	IEEE Xplore Digital Library
Author	Takeuchi, K. Chang, K. Zhang, K. Yamauchi, T. Gastaldi, R.
Copyright Year	2011
Description	Author affiliation: University of Tokyo, Tokyo, Japan (Takeuchi, K.; Zhang, K.) \|\| Intel, Hillsboro, OR (Gastaldi, R.) \|\| Xilinx, San Jose, CA (Chang, K.; Yamauchi, T.)
Abstract	Energy efficient VLSIs with an ultra-low voltage power supply down to 0.5V are in growing demand in various applications, e.g., secure card, sensor node, and medical systems where power is supplied by RF wave, solar cells and small batteries. Various technological challenges, including PVT variations, low operating voltage margin, increased stand-by power consumption and low driving current, must be addressed. This forum provides an overview of the technical challenges as well as most recent circuit advances in key building blocks for digital/analog VLSI applications. The forum starts with the overview on microprocessor design for smarphones. The microprocessor used in personal computers is redesigned and optimized, delivering over 2–4x performance in the smartphone power envelope. High performance and variability resistant device technologies are presented for low power and multimedia products operating at very low V. The forum also has three presentations to discuss the design challenges for logic and memory in scaled technologies with increased parameter variations. For the digital design, pitfalls in deep-low-voltage circuits are summarized with emphasis on V issues with experimental results. SRAM design trade-offs with respect to area, read/write stability, and access time are discussed for different applications. Embedded non-volatile memory with zero power is also presented. Design tradeoffs involved in building blocks for low-power signal path along with on-die voltage regulators are discussed. Key analog circuits such as low-voltage voltage generator, VCO, PLL, ADC and DAC are examined for voltage scaling. Conventional bangap reference is no longer feasibile down to 0.5V regime. Different low-voltage voltage generator circuits and their pros and cons will be discussed. The impact of V scaling on the various performance metrics for timing related circuits, such as voltage-controlled oscillators and phase-locked loops is presented with an emphasis on their application in input/output interfaces. Low-voltage data converters are reviewed, covering the current status, enhancement solutions and future direction for higher energy efficiency.
Starting Page	514
Ending Page	515
File Size	1348140
Page Count	2
File Format	PDF
ISBN	9781612843032
ISSN	01936530
e-ISBN	9781612843025
DOI	10.1109/ISSCC.2011.5746429
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Awards activities Computers CMOS integrated circuits Computer architecture Very large scale integration Semiconductor device modeling Solid state circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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