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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Takashima, D. Noguchi, M. Shibata, N. Kanda, K. Sukegawa, H. Fujii, S. |
| Copyright Year | 2011 |
| Description | Author affiliation: Toshiba, Yokohama, Japan (Takashima, D.; Noguchi, M.; Shibata, N.; Kanda, K.; Sukegawa, H.; Fujii, S.) |
| Abstract | The increase of NAND flash memory capacity has strongly contributed to market growth of a variety of mobile equipment such as visual/audio electronics, smart phones, and SSD/USB devices. This memory capacity increase up to 64Gb [1] is attributed to multi-level cell (MLC) technology up to 4b/cell as well as shrinking process. However, the realization of MLC requires tight cell V distribution by the precise and gradual programming [2] and pre-programming to the neighboring wordlines to compensate the floating-gate coupling [1,3]. This gives rise to poor program throughput due to long program time when increasing from 1b/cell to 4b/cell, as shown in Fig. 28.9.1(a). Therefore, a lot of page buffers beside a cell array have been introduced to increase the number of simultaneously programmed cells to maintain the program throughput. Moreover, multiple data latches in a page buffer are required to latch all bits from/to each MLC [3], as shown in Fig. 28.9.1(b). Consequently, the total page buffer size per chip has increased remarkably and has reached 64KB (512Kb) in a 4b/cell 64Gb chip as shown in Fig. 28.9.1(c). These results imply that numerous page buffers based on SRAM flip-flops are mandatory and their area overhead is a serious problem in scaled NAND flash memories. |
| Starting Page | 504 |
| Ending Page | 505 |
| File Size | 2887052 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781612843032 |
| ISSN | 01936530 |
| e-ISBN | 9781612843025 |
| DOI | 10.1109/ISSCC.2011.5746417 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-02-20 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Flash memory Random access memory Capacitance MOS capacitors Transistors Couplings Sensors |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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