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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sinangil, M.E. Mair, H. Chandrakasan, A.P. |
| Copyright Year | 2011 |
| Description | Author affiliation: Massachusetts Institute of Technology, Cambridge, MA (Sinangil, M.E.; Chandrakasan, A.P.) || Texas Instruments, Dallas, TX (Mair, H.) |
| Abstract | An increasing amount of embedded memory is used in today's ICs and consequently the design of low-power, high-density SRAM is becoming critical. With technology scaling, it is becoming increasingly more challenging to achieve reliable low voltage operation for SRAMs due to process variation. Recent work proposed various design innovations to address this problem [1–2]. Conventional 6T SRAM bit-cell provides high area density but fails to operate as supply voltage scales down. Instead, the work in [3] utilizes an asymmetrical 6T bit-cell that can operate down to 0.7V in 45nm CMOS. An alternative 8T bit-cell topology can potentially operate at lower V [4–5], yet it leads to ∼40% larger bit-cell area and suffers from half-select problem if used in a column-interleaved architecture. In this work, we present a 28nm high-density 6T SRAM operating down to low supply voltages. Hierarchical bit-line architecture, pre-read phase during write cycles and signal boosting for better write-ability provide functionality down to 0.6V. Figure 14.4.1 shows an SEM image of the 6T bit-cell used in this work. This bit-cell has an area of $0.12μm^{2}$ providing very high transistor density. |
| Starting Page | 260 |
| Ending Page | 262 |
| File Size | 2666117 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781612843032 |
| ISSN | 01936530 |
| e-ISBN | 9781612843025 |
| DOI | 10.1109/ISSCC.2011.5746310 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-02-20 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Computer architecture Sensors Inverters Boosting Microprocessors MOS devices |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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