NDLI: Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor

Content Provider	IEEE Xplore Digital Library
Author	Pelella, A.R. Chan, Y.H. Balakrishnan, B. Patel, P. Rodko, D. Serton, R.E.
Copyright Year	2011
Description	Author affiliation: IBM Systems and Technology Group, Poughkeepsie, NY (Pelella, A.R.; Chan, Y.H.; Balakrishnan, B.; Patel, P.; Rodko, D.; Serton, R.E.)
Abstract	With the push to ever higher core frequencies, more logic functions are making their way onto critical path SRAMs in the L1 cache look up structure. Described in this paper is a 14 bit dynamic hit logic scheme with an embedded 8K bit SRAM in IBM's 45nm SOI [3]. The hit logic uses a “search-for-a-hit” scheme (i.e., XOR's followed by AND functions, pre-charged to a miss) to provide optimal performance, timing, and power. A custom microcode programmable Array-Built-In-Self-Test (ABIST) engine tests both the SRAM and hit logic function jointly, resulting in comprehensive “at-speed” test coverage to guarantee circuit functionality and timing margins. The SRAM is organized as a 64×15b×8W (way, or set) array and uses a 6T SRAM cell (1Read/1Write, $0.462μm^{2})$ in a “domino” hierarchal dual read bitline approach [1]
Starting Page	72
Ending Page	73
File Size	351540
Page Count	2
File Format	PDF
ISBN	9781612843032
ISSN	01936530
e-ISBN	9781612843025
DOI	10.1109/ISSCC.2011.5746224
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Logic gates Latches Driver circuits Arrays Delay
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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