NDLI: A 570fs integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop

Content Provider	IEEE Xplore Digital Library
Author	Sai, A. Yamaji, T. Itakura, T.
Copyright Year	2011
Description	Author affiliation: Toshiba, Kawasaki, Japan (Sai, A.; Yamaji, T.; Itakura, T.)
Abstract	Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fs integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase noise characteristic as compared to an LC VCO, but its area efficiency is attractive. To suppress the phase noise of a ring VCO, a wide-loop-bandwidth PLL with sufficiently low in-band noise is indispensable. An all-digital PLL (ADPLL) [2] has insufficiently low in-band phase noise because of the quantization error of the time-to-digital converter (TDC) without employing additional techniques such as power-hungry time amplification [3]. On the other hand, a conventional analog PLL has a superior in-band phase noise but needs a large loop-filter capacitor to maintain a wide tuning range due to a high control sensitivity of the ring VCO. The dual-tuning topology is useful for minimizing the size of the loop filter while maintaining low in-band phase noise [4, 5]. However, it also suffers from strong reference spurs, as it is the case in the conventional analog PLL having a wide loop bandwidth. The proposed PLL employs a hybrid loop consisting of a type-II ADPLL and a type-I analog PLL. The type-II ADPLL enables the wide tuning range without a large loop-filter capacitor. The loop-filter capacitor in the analog PLL is also minimized since it does not need to cover a wide tuning range. The analog PLL eliminates the residual quantization error of the TDC in the ADPLL and achieves a sufficiently low in-band phase noise. Overall, the proposed PLL suppresses the phase noise contribution from the ring digital/voltage-controlled oscillator (DVCO).
Starting Page	98
Ending Page	100
File Size	1044211
Page Count	3
File Format	PDF
ISBN	9781612843032
ISSN	01936530
e-ISBN	9781612843025
DOI	10.1109/ISSCC.2011.5746236
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Phase noise Phase frequency detector Image edge detection Tuning Voltage-controlled oscillators
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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