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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Seung-Jun Bae Young-Soo Sohn Tae-Young Oh Si-Hong Kim Yun-Seok Yang Dae-Hyun Kim Sang-Hyup Kwak Ho-Seok Seol Chang-Ho Shin Min-Sang Park Gong-Heom Han Byeong-Cheol Kim Yong-Ki Cho Hye-Ran Kim Su-Yeon Doo Young-Sik Kim Dong-Seok Kang Young-Ryeol Choi Sam-Young Bang Sun-Young Park Yong-Jae Shin Gil-Shin Moon Cheol-Goo Park Woo-Seop Kim Hyang-Ja Yang Jeong-Don Lim Kwang-Il Park Joo Sun Choi Young-Hyun Jun |
| Copyright Year | 2011 |
| Description | Author affiliation: Samsung Electronics, Hwasung, Korea (Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; Yong-Ki Cho; Hye-Ran Kim; Su-Yeon Doo; Young-Sik Kim; Dong-Seok Kang; Young-Ryeol Choi; Sam-Young Bang; Sun-Young Park; Yong-Jae Shin; Gil-Shin Moon; Cheol-Goo Park; Woo-Seop Kim; Hyang-Ja Yang; Jeong-Don Lim; Kwang-Il Park; Joo Sun Choi; Young-Hyun Jun) |
| Abstract | Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization [1–3]. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator. |
| Starting Page | 498 |
| Ending Page | 500 |
| File Size | 1897209 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781612843032 |
| ISSN | 01936530 |
| e-ISBN | 9781612843025 |
| DOI | 10.1109/ISSCC.2011.5746414 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-02-20 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Crosstalk Equalizers Jitter Driver circuits Phase locked loops Random access memory Clocks |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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