NDLI: Surface-micromachined deep back chamber MEMS acoustic sensor using two sacrificial layers

Content Provider	IEEE Xplore Digital Library
Author	Jaewoo Lee Ko, S.C. Song, H.W. Park, K.-H. Jongdae Kim
Copyright Year	2008
Description	Author affiliation: Convergence Components & Mater. Res. Lab., Electron. & Telecommun. Res. Inst., Daejeon (Jaewoo Lee; Ko, S.C.; Song, H.W.; Park, K.-H.; Jongdae Kim)
Abstract	A deep back chamber micro-electro-mechanical system (MEMS) acoustic sensor with two sacrificial layers based on surface micromachining on a GaAs substrate is presented. As it is designed to be implemented on only the front side of a substrate in order to satisfy the need for a simple monolithic integrated process, this sensor has bottom electrode anchors fabricated using the first sacrificial layer for the formation of a back chamber. Each bottom electrode anchor, with a rectangular area of 50 mum times 50 mum, enables the bottom electrode to act as a stiff back plate because it make the bottom electrode fix onto a substrate through the patterning of the first sacrificial layer. The circular-shape MEMS acoustic sensor proposed in this paper has a membrane diameter of 1.0 mm and a back chamber total depth of 11.5 mum. It shows a pull down voltage of 9.7 V and a zero-bias sensor capacitance $(C_{S0})$ of 2.9 pF at 1 KHz. Additionally, the sensor has an open-circuit sensitivity of 0.08 mV/Pa at 1 KHz with a bias of 1.5 V.
Starting Page	569
Ending Page	572
File Size	1043975
Page Count	4
File Format	PDF
ISBN	9781424425808
ISSN	19300395
DOI	10.1109/ICSENS.2008.4716503
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Micromechanical devices Acoustic sensors Electrodes Microelectromechanical systems Micromachining Gallium arsenide Biomembranes Voltage Capacitive sensors Capacitance
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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