NDLI: FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Applications

Content Provider	IEEE Xplore Digital Library
Author	Benhamid, M. Othman, M.
Copyright Year	2006
Description	Author affiliation: Univ. Kebangsaan Malaysia, Bangi (Benhamid, M.; Othman, M.)
Abstract	This paper proposes a novel fully parallel FFT architecture based on canonical signed digit (CSD) multiplier-less targeting wireless communication applications, such as IEEE802.15.3a wireless personal area network (WPAN) baseband. The proposed architecture has the advantages of high throughput, less latency, and smaller area. The multiplier-less architecture uses shift- and-add operations to realize the complex multiplier and uses the CSD to optimize these operations. The design has been coded in Verilog HDL targeting Xilinx Virtex-II FPGA series. It is fully implemented and tested on real hardware using Virtex-II FG456 prototype board. Based on this architecture, the implementation of 8-points FFT on Virtex-II can run at a maximum clock frequency of about 400 MHz which lead to about 3.2 GS/s throughput with a latency of 6 clock cycles using 16,580 equivalent gates. Comparison with a conventional parallel architecture design of the same size can run only at a maximum clock frequency of 220 MHz or 1.76 GS/s throughput with a latency of 12 clock cycles using 77,418 equivalent gates for the design. The resulting throughput increases by about 82% while the equivalent gates and latency decrease by about 79% and 50% respectively.
Starting Page	641
Ending Page	645
File Size	2537364
Page Count	5
File Format	PDF
ISBN	0780397304
DOI	10.1109/SMELEC.2006.380712
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-29
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Wireless communication Throughput Delay Clocks Hardware design languages Frequency Wireless personal area networks Baseband Testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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