NDLI: Design of 100nm Single-Electron Transistor (SET) by 2D TCAD Simulation

Content Provider	IEEE Xplore Digital Library
Author	Rasmi, A. Hashim, U. Awang Mat, A.F.
Copyright Year	2006
Description	Author affiliation: UPM-MTDC, Serdang (Rasmi, A.)
Abstract	One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with 100 nm gate length and 10 nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 times $10^{-9}$ Watt for fixed current and 3.3565 times $10^{-9}$ Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation.
Starting Page	367
Ending Page	372
File Size	2204536
Page Count	6
File Format	PDF
ISBN	0780397304
DOI	10.1109/SMELEC.2006.381083
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-29
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Single electron transistors Medical simulation Integrated circuit technology Large scale integration Capacitance Single electron devices Nanoscale devices Low voltage Impedance FETs
Content Type	Text
Resource Type	Article

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Design of 100nm Single-Electron Transistor (SET) by 2D TCAD Simulation