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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jia Huo Guochu Shou Yihong Hu Zhigang Guo |
| Copyright Year | 2009 |
| Abstract | In this paper, we propose a high-speed parallel 128 bit multiplier for Ghash Function in conjunction with its FPGA implementation. Through the use of Verilog the designs are evaluated by using Xilinx Vertax5 with 65nm technic and 30,000 logic cells. The highest throughput of 30.764Gpbs can be achieved on virtex5 with the consumption of 8864 slices LUT. The proposed design of the multiplier can be utilized as a design IP core for the implementation of the Ghash Function. The architecture of the multiplier can also apply in more general polynomial basis. Moreover it can be used as arithmetic module in other encryption field. |
| Starting Page | 554 |
| Ending Page | 557 |
| File Size | 532192 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424442232 |
| DOI | 10.1109/NSWCTC.2009.96 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-25 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay effects FPGA implementation Throughput Ghash Galois fields compoent multiplaier Wireless communication Application specific integrated circuits Polynomials Cryptography Hardware design languages Field programmable gate arrays Arithmetic |
| Content Type | Text |
| Resource Type | Article |
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