NDLI: Application of Autosched AP Simulation Model in Wafer Fab

Content Provider	IEEE Xplore Digital Library
Author	Tien, V.S.Y. Yeo Eng Teck Govindasamy, G.D. Kamaruddin, S.
Copyright Year	2006
Description	Author affiliation: Silterra Malaysia Sdn Bhd, Kulim (Tien, V.S.Y.; Yeo Eng Teck; Govindasamy, G.D.)
Abstract	Wafer fabrication or "fab" simulation models are often used to assist the daily running of wafer production. Their main uses have been focused on testing production scenarios, to estimate cycle times, quote delivery times to customers, or test operational policies such as lot dispatching rules and material handling systems scheduling policies. Fab technologies sometimes stay in demand for as little as one year, after that wafer prices often drop rapidly. Based on this, many semiconductor manufacturers regard cycle time as the most important element and treat it as a monitored performance measure in wafer fabrication. One of the significant benefits of simulation modeling is the ability to conduct sensitivity ("What-If") analyses that allow us to experiment without disrupting the actual manufacturing operation. This paper will focus on and present the applications of the Autosched AP simulation software from Brooks Automation to provide ("What-IP') analysis and a characteristic curve relating Cycle time to Fab Utilization. The paper will show how simulation is used as a modeling tool to assist a production manager's decision-making process in production planning and effectively evaluate the factory's performance capabilities. Analysis will describe the impact of different percentage of factory loading on the cycle time.
Starting Page	846
Ending Page	850
File Size	2082558
Page Count	5
File Format	PDF
ISBN	0780397304
DOI	10.1109/SMELEC.2006.380757
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-29
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Fabrication Materials testing System testing Semiconductor device manufacture Analytical models Production systems Dispatching Materials handling Job shop scheduling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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