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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dayeh, S.A. Susac, D. Peng Chen Yi Jing Kavanagh, K.L. Lau, S.S. Yu, E.T. Deli Wang |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of California-San Diego, La Jolla, CA (Dayeh, S.A.) |
| Abstract | We present new fundamental insights into the nucleation and evolution of InAs nanowires (NWs) grown using organo-metallic vapor-phase epitaxy (OMVPE), the correlation of their room temperature transport behavior with their structural properties, and a novel scheme for their integration to Si substrates. We experimentally distinguish, for the first time, two NW growth regimes defined by the direction of In adatom exchange between the NW (InAs) and the substrate (InAs (lll)B). This understanding leads to optimal control over the NW morphology over length scales of the order of the In adatom surface diffusion length on the NW sidewalls. Transmission electron microscopy (TEM) analysis of the NW crystal structure of wurtzite (WZ) and zincblende (ZB) NWs is used to explain striking differences in their transport behavior. We find that the presence of small ZB sections in the WZ NWs can create spontaneous polarization sheet charges at each section interface along the NW channel, leading to improved subthreshold characteristics over those of pure ZB NWs, as observed in our electrical device measurements. Finally, we successfully demonstrate the vertical integration of electrically isolated InAs NWs on $SiO_{2}$ on Si suitable for implementing 3D NW circuits using the bottom-up synthesis approach for practical integration of III-V functional devices to Si technology. |
| Starting Page | 576 |
| Ending Page | 579 |
| File Size | 851739 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421039 |
| DOI | 10.1109/NANO.2008.170 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-18 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Substrates Silicon Surface morphology FETs Gold Optimal control Correlation |
| Content Type | Text |
| Resource Type | Article |
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