NDLI: UI-Timer: An ultra-fast clock network pessimism removal algorithm

Content Provider	IEEE Xplore Digital Library
Author	Tsung-Wei Huang Pei-Ci Wu Wong, M.D.F.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Tsung-Wei Huang; Pei-Ci Wu; Wong, M.D.F.)
Abstract	The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper UI-Timer, a powerful CNPR algorithm which achieves exact accuracy and ultra-fast runtime. Unlike existing approaches which are dominated by explicit path search, UI-Timer proves that by implicit path representation the amount of search effort can be significantly reduced. Our timer is superior in both space and time saving, from which memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 CAD contest have justified that UI-Timer achieved the best result in terms of accuracy and runtime over all participating timers.
Starting Page	758
Ending Page	765
File Size	833336
Page Count	8
File Format	PDF
ISBN	9781479962785
DOI	10.1109/ICCAD.2014.7001436
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Design automation Runtime Indexes Algorithm design and analysis
Content Type	Text
Resource Type	Article

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