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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yu-Hsuan Su Yu-Chen Huang Liang-Chun Tsai Yao-Wen Chang Banerjee, S. |
| Copyright Year | 2014 |
| Description | Author affiliation: Samsung Accel., New York, NY, USA (Banerjee, S.) || Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Yu-Hsuan Su; Yu-Chen Huang; Yao-Wen Chang) || Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Liang-Chun Tsai) |
| Abstract | As nanometer technology advances, conventional OPC (Optical Proximity Correction) that minimizes the EPE (Edge Placement Error) at the nominal corner alone often leads to poor process window. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process-variation-aware mask optimization framework, namely PVOPC (Process-Variation OPC), to simultaneously minimize EPE and PV (Process-Variation) band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, process-variation-aware EPE modeling, and post correction with three new EPE-converging techniques and a systematic sub-resolution assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results. |
| Starting Page | 230 |
| Ending Page | 237 |
| File Size | 1736203 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781479962785 |
| DOI | 10.1109/ICCAD.2014.7001357 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-11-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Image segmentation Layout Optimization Process control Convergence Systematics Lithography |
| Content Type | Text |
| Resource Type | Article |
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