NDLI: Constrained interpolation for guided logic synthesis

Content Provider	IEEE Xplore Digital Library
Author	Petkovska, A. Novo, D. Mishchenko, A. Ienne, P.
Copyright Year	2014
Description	Author affiliation: Sch. of Comput. & Commun. Sci., Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland (Petkovska, A.; Novo, D.; Ienne, P.) \|\| Dept. of EECS, Univ. of California, Berkeley, Berkeley, CA, USA (Mishchenko, A.)
Abstract	Craig interpolation is a known method for expressing a target function f as a function of a given set of base functions G. The resulting interpolant represents the dependency function h, such that f = h(G). Generally, the set G contains enough base functions to enable the existence of multiple dependency functions whose quality mainly depends on which base functions were selected for reconstruction. The interpolation is not an optimisation problem and thus, often, it selects some random base functions and, particularly, omits others potentially required for an optimal implementation of the target function. Mainly, it is impossible to impose that the interpolant uses a specific base function. In this paper, we propose a method that forces a specific base function $g_{i}$ as a primary input of a dependency function. Such a dependency function is built as a Shannon expansion of two constrained Craig interpolants for the assignments of the primary inputs for which $g_{i}$ evaluates to 0 and 1, respectively. We also introduce a method that iteratively imposes a predefined set of base functions. In each iteration, we generate a new dependency function for use as the target function of the next iteration in order to force the use of a base function. We show that, unlike the standard Craig interpolation method, our carving method succeeds to impose the desired base functions with very high probability. It recomposes single-output logic circuits as their delay- or area-optimised implementations regardless of the input implementation. The proposed methods can be efficiently employed for rewriting circuits in some synthesis-based algorithms.
Starting Page	462
Ending Page	469
File Size	1158526
Page Count	8
File Format	PDF
ISBN	9781479962785
DOI	10.1109/ICCAD.2014.7001392
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interpolation Standards Vectors Logic gates Logic circuits Boolean functions Optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Realizing reversible circuits using a new class of quantum gates

Majority logic gate synthesis approaches for post-CMOS logic circuits: A review

Boolean matching in logic synthesis

Minimal logic re-synthesis for engineering change

A Synthesis Flow for Sequential Reversible Circuits

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits

Constrained interpolation for guided logic synthesis

Coalgebraic division for multilevel logic synthesis

Reduction of interpolants for logic synthesis

Constrained interpolation for guided logic synthesis

Similar Documents

Realizing reversible circuits using a new class of quantum gates

Majority logic gate synthesis approaches for post-CMOS logic circuits: A review

Boolean matching in logic synthesis

Minimal logic re-synthesis for engineering change

A Synthesis Flow for Sequential Reversible Circuits

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits

Constrained interpolation for guided logic synthesis

Coalgebraic division for multilevel logic synthesis

Reduction of interpolants for logic synthesis

Constrained interpolation for guided logic synthesis