NDLI: Sub-20 nm design technology co-optimization for standard cell logic

Content Provider	IEEE Xplore Digital Library
Author	Vaidyanathan, K. Liebmann, L. Strojwas, A. Pileggi, L.
Copyright Year	2014
Description	Author affiliation: IBM, East Fishkill, NY, USA (Liebmann, L.) \|\| Carnegie Mellon Univ., Pittsburgh, PA, USA (Vaidyanathan, K.; Strojwas, A.; Pileggi, L.)
Abstract	Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTCO) for standard cell logic. In our holistic DTCO we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTCO in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.
Starting Page	124
Ending Page	131
File Size	3412840
Page Count	8
File Format	PDF
ISBN	9781479962785
DOI	10.1109/ICCAD.2014.7001342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Microprocessors Standards CMOS integrated circuits Rails Layout Gratings Multiple patterning Standard cell logic 14 nm CMOS Design Technology Co-Optimization FinFET device
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in