NDLI: A hierarchical approach for generating regular floorplans

Content Provider	IEEE Xplore Digital Library
Author	de San Pedro, J. Cortadella, J. Roca, A.
Copyright Year	2014
Description	Author affiliation: Univ. Politec. de Catalunya, Barcelona, Spain (de San Pedro, J.; Cortadella, J.; Roca, A.)
Abstract	The complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more reusable parts. In this work we introduce HiReg, a new floorplanning algorithm that generates regular floorplans. HiReg automatically extracts repeating patterns in a design by using graph mining techniques. Regularity is exploited by reusing the same floorplan for multiple instances of a pattern, as long as neither area, wire length or existing hierarchy constraints are violated or compromised. The proposed scheme is targeted towards early system-level design of chip multiprocessors (CMPs). Experiments show the scalability of the method for many-core CMPs and competitive results in area and wire length.
Starting Page	655
Ending Page	662
File Size	979279
Page Count	8
File Format	PDF
ISBN	9781479962785
DOI	10.1109/ICCAD.2014.7001422
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Complexity theory Wires Measurement Wiring Algorithm design and analysis Scalability Planning
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A hierarchical approach for generating regular floorplans

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules

A new join-less approach for co-location pattern mining

Hierarchical Global Wiring for Custom Chip Design

SLOAVx: Scalable LOgarithmic AlltoallV Algorithm for Hierarchical Multicore Systems

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

A hierarchical framework to enhance scalability and performance of scheduling and mapping algorithms

Path planning based on Constrained Delaunay Triangulation

Generation of Layouts from MOS Circuit Schematics: A Graph Theoretic Approach

A hierarchical approach for generating regular floorplans

Similar Documents

A hierarchical approach for generating regular floorplans

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules

A new join-less approach for co-location pattern mining

Hierarchical Global Wiring for Custom Chip Design

SLOAVx: Scalable LOgarithmic AlltoallV Algorithm for Hierarchical Multicore Systems

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

A hierarchical framework to enhance scalability and performance of scheduling and mapping algorithms

Path planning based on Constrained Delaunay Triangulation

Generation of Layouts from MOS Circuit Schematics: A Graph Theoretic Approach

A hierarchical approach for generating regular floorplans