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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Maksimovic, D. Bao Le Veneris, A. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada (Maksimovic, D.; Bao Le; Veneris, A.) |
| Abstract | Modern designs are growing in size and complexity, becoming increasingly harder to verify. Today, they are architected to include multiple clock domains as a measure to reduce power consumption. Verifying them proves to be a computationally intensive and challenging task as it requires their clocks to be synchronized. To achieve synchronization, existing Boolean satisfiability-based methodologies add hardware to combine the clock domains before transforming them into their iterative logic array representation (ILA). As a consequence, this results in the addition of redundant time-frames adding overhead during verification. This paper introduces a novel framework to verify designs with multiple clocks using Quantified Boolean Formula satisfiability (QBF). We first present a formulation that models an ILA representation with symbolic universal quantification to achieve synchronization. This is later extended with the use of a clock divider to overcome inefficiencies. The net effect is the reduction in the number of redundant time-frames. Furthermore, the usage of QBF results in significant memory savings when compared to traditional methods. Experiments on bounded model checking demonstrate memory reductions of 76% on average with competitive run-time performance. |
| Starting Page | 684 |
| Ending Page | 689 |
| File Size | 588639 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479962785 |
| DOI | 10.1109/ICCAD.2014.7001426 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-11-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Synchronization Clocks Multiplexing Arrays Hardware Memory management Frequency-domain analysis |
| Content Type | Text |
| Resource Type | Article |
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