NDLI: Full chip impact study of power delivery network designs in monolithic 3D ICs

Content Provider	IEEE Xplore Digital Library
Author	Samal, S.K. Samadi, K. Kamal, P. Du, Y. Sung Kyu Lim
Copyright Year	2014
Description	Author affiliation: Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA (Samal, S.K.; Sung Kyu Lim) \|\| Qualcomm Res., San Diego, CA, USA (Samadi, K.; Kamal, P.; Du, Y.)
Abstract	In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in monolithic 3D ICs. Our studies first show that the full PDN worsens routing congestion more severely in monolithic 3D ICs than in 2D designs due to the significant reduction in resources for 3D connections. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues in 3D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in monolithic 3D ICs than TSV-based 3D and 2D designs. This is because of the higher integration density and the severe competition between signal and power connections. Lastly, we develop various PDN design optimization techniques for monolithic 3D ICs and obtain up to 8% signal wirelength and 5% maximum temperature reduction under the given IR drop budget.
Starting Page	565
Ending Page	572
File Size	3143467
Page Count	8
File Format	PDF
ISBN	9781479962785
DOI	10.1109/ICCAD.2014.7001406
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Metals Routing Wires Conductivity Integrated circuits Power dissipation
Content Type	Text
Resource Type	Article

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