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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Haitong Tian Yuelin Du Hongbo Zhang Zigang Xiao Wong, M.D.F. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana Champaign, Champaign, IL, USA (Haitong Tian; Yuelin Du; Zigang Xiao; Wong, M.D.F.) || Synopsys Inc., Mountain View, CA, USA (Hongbo Zhang) |
| Abstract | Triple patterning lithography (TPL) has been recognized as one of the most promising techniques for 14/10nm technology node. There are various concerns for TPL decompositions. For standard cell based designs, assigning the same pattern for the same type of cells is a desired property for TPL decomposition. It is more robust for process variations and gives the chip similar physical and electrical characteristics as well as more reliable and predictable performance. Assigning the same type of pattern for the same type of cell is called a constrained pattern assignment (CPA) problem. In this paper, we integrated the flow of detailed placement and TPL decompositions with CPA coloring constraints. We focused on refining a layout to make it CPA-friendly during the detailed placement stage while minimizing the area and HPWL (half perimeter wire length) overhead. A weighted partial MAX SAT approach is proposed which guarantees to obtain a CPA-friendly detailed placement result while minimizing the area overhead. An efficient graph model is also proposed to compute the locations of the cells with optimal HPWL. Our formulation is very efficient and achieves a 79.4% area overhead reduction compared with the approach of fixing cell colors beforehand. Better HPWL are also achieved consistently over all benchmarks. |
| Starting Page | 116 |
| Ending Page | 123 |
| File Size | 810854 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781479962785 |
| DOI | 10.1109/ICCAD.2014.7001341 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-11-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Layout Standards Law Lithography Color Algorithm design and analysis |
| Content Type | Text |
| Resource Type | Article |
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