NDLI: Protecting SRAM-based FPGAs against multiple bit upsets using erasure codes

Content Provider	IEEE Xplore Digital Library
Author	Rao, P.M.B. Ebrahimi, M. Seyyedi, R. Tahoori, M.B.
Copyright Year	2014
Description	Author affiliation: Karlsruhe Inst. of Technol., Karlsruhe, Germany (Rao, P.M.B.; Ebrahimi, M.; Seyyedi, R.; Tahoori, M.B.)
Abstract	Multiple bit upsets due to radiation-induced soft errors are a major concern in nanoscale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. The combination of error correction schemes and configuration scrubbing is an efficient approach to avoid such permanent errors. Existing solutions exploit coding techniques with considerably high overhead to protect configuration frames against multiple bit upsets. In this paper, we propose a generic scrubbing scheme which reconstructs the erroneous configuration frame based on the concept of erasure codes. Our proposed scheme does not require any changes to the FPGA architecture. Experimental results on a Xilinx Virtex-6 FPGA device show that the proposed scheme achieves error recovery coverage of 99.30% with only 3% resource occupation while the mean time to repair is comparable with previous schemes.
Starting Page	1
Ending Page	6
File Size	1009372
Page Count	6
File Format	PDF
ISBN	9781479930173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Field programmable gate arrays Encoding Error correction codes Decoding Error correction Performance evaluation Random access memory
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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