NDLI: An HDL-based system design methodology for multistandard RF SoC's

Content Provider	IEEE Xplore Digital Library
Author	Atac, A. Zhimiao Chen Lei Liao Yifan Wang Schleyer, M. Ye Zhang Wunderlich, R. Heinen, S.
Copyright Year	2014
Description	Author affiliation: Integrated Analog Circuit & RF Syst., RWTH Aachen Univ., Aachen, Germany (Atac, A.; Zhimiao Chen; Lei Liao; Yifan Wang; Schleyer, M.; Ye Zhang; Wunderlich, R.; Heinen, S.)
Abstract	Multistandard SoC's including advanced RF and analog circuitry with digital blocks are pervasive in modern IC's. However, the system design and verification methodologies that capture the complexity of multistandard RF SoC's are still limited. In this paper, an HDL design methodology is introduced for multistandard RF SoC's, which covers all the design layers from system design, to automatic extraction of the models from circuits and a systematic top level verification. The offered HDL based design methodology combines top down and bottom up design approaches, and brings the design and verification closer by reflecting the circuits to models automatically via an Automatic Parameter Extraction (APX) tool. System or block level verification is obtained with models automatically by overnight runs, without the need for extra test benches or designer interaction. This enables short term detection of functional errors or performance losses. A first time tape out of a multimode Bluetooth transceiver SoC is designed and fabricated in 8 months by using the offered methodology. The accuracy of the system level simulations show a very good match with the measurement results after fabrication. The test SoC is fabricated with 0.13 μm CMOS technology.
Starting Page	1
Ending Page	6
File Size	260112
Page Count	6
File Format	PDF
ISBN	9781479930173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	System-on-chip Hardware design languages Integrated circuit modeling Radio frequency Transistors Design methodology Receivers Bluetooth Low Energy SoC RF SoC SoC design system methodology analog modeling SoC verification Bluetooth
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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