NDLI: Early-stage power grid design: Extraction, modeling and optimization

Content Provider	IEEE Xplore Digital Library
Author	Cheng Zhuo Houle Gan Wei-Kai Shih
Copyright Year	2014
Description	Author affiliation: Intel Corp., Hillsboro, OR, USA (Cheng Zhuo; Houle Gan; Wei-Kai Shih)
Abstract	Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design database is NOT complete, including extraction, modeling and optimization. This paper tackles these fundamental issues of early-stage power grid design. The proposed methods have been silicon-validated on 32nm on-market chips and successfully applied to a 22nm design for its early stage power grid design. The findings from such practices reveal that, for sub-32nm chips, intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and need to be well addressed at early stage.
Starting Page	1
Ending Page	6
File Size	1314845
Page Count	6
File Format	PDF
ISBN	9781479930173
DOI	10.1145/2593069.2593129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power grids Optimization Logic gates Couplings Wires Rails Metals
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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